The present application relates to a semiconductor structure, and particularly to stacked nanowire field effect transistors with reduced gate resistance and methods of manufacturing the same.
Semiconductor devices employing a semiconductor nanowire, such as nanowire field effect transistor (FETs), provide a tight control of the channel, enabling suppression of off-current at a level not possible with conventional fin FETs. However, nanowire FETs usually offer less on-current density for a given chip area than conventional fin FETs.
On way to increase the on-current density of nanowire FETs is to form a vertical stack of semiconductor nanowires. However, the narrow spacing (typically in the order of 5 nm-10 nm) between stacked semiconductor nanowires makes it difficult to fill in the spaces with a low resistance metal, such as tungsten, when forming gate structures, resulting in high gate resistance in stacked nanowire FETs. Therefore, there remains a need to reduce the gate resistance of certain high performance nanowire FETs for high-frequency applications.